Deferring loads and stores when a load buffer or store buffer fills during execute-ahead mode

ABSTRACT

One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. Next, the system executes the instruction and subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order. Upon encountering a store during the execute-ahead mode, the system determines if the store buffer is full. If so, the system prefetches a cache line for the store, and defers execution of the store.

RELATED APPLICATION

This application is a continuation-in-part of, and hereby claims priority under 35 U.S.C. §120 to, a U.S. patent application, entitled “Selectively Deferring the Execution of Instructions with Unresolved Data Dependencies as They Are Issued in Program Order,” by inventors Shailender Chaudhry, Marc Tremblay and Quinn Jacobson, Ser. No. 10/686,061, filed 14 Oct. 2003 now U.S. Pat. No. 7,114,060. This application also claims priority under 35 U.S.C. §119 to U.S. Provisional Patent Application No. 60/562,835 filed on 15 Apr. 2004, entitled “Deferring Loads and Stores When a Load Buffer or Store Buffer Fills During Execute-Ahead Mode,” by inventors Shailender Chaudhry, Paul Caprioli and Marc Tremblay.

BACKGROUND

1. Field of the Invention

The present invention relates to techniques for improving the performance of computer systems. More specifically, the present invention relates to a method and an apparatus for deferring loads and stores when a load buffer or a store buffer becomes full during execute-ahead mode.

2. Related Art

Advances in semiconductor fabrication technology have given rise to dramatic increases in microprocessor clock speeds. This increase in microprocessor clock speeds has not been matched by a corresponding increase in memory access speeds. Hence, the disparity between microprocessor clock speeds and memory access speeds continues to grow, and is beginning to create significant performance problems. Execution profiles for fast microprocessor systems show that a large fraction of execution time is spent not within the microprocessor core, but within memory structures outside of the microprocessor core. This means that the microprocessor systems spend a large fraction of time waiting for memory references to complete instead of performing computational operations.

Efficient caching schemes can help reduce the number of memory accesses that are performed. However, when a memory reference, such as a load operation generates a cache miss, the subsequent access to level-two (L2) cache or memory can require dozens or hundreds of clock cycles to complete, during which time the processor is typically idle, performing no useful work.

A number of techniques are presently used (or have been proposed) to hide this cache-miss latency. Some processors support out-of-order execution, in which instructions are kept in an issue queue, and are issued “out-of-order” when operands become available. Unfortunately, existing out-of-order designs have a hardware complexity that grows quadratically with the size of the issue queue. Practically speaking, this constraint limits the number of entries in the issue queue to one or two hundred, which is not sufficient to hide memory latencies as processors continue to get faster. Moreover, constraints on the number of physical registers that are available for register renaming purposes during out-of-order execution also limits the effective size of the issue queue.

Some processor designers have proposed entering a “scout mode” during processor stall conditions. In this scout mode, instructions are speculatively executed to prefetch future loads, but results are not committed to the architectural state of the processor. For example, see U.S. patent application Ser. No. 10/741,944, filed 19 Dec. 2003, entitled, “Generating Prefetches by Speculatively Executing Code through Hardware Scout Threading,” by inventors Shailender Chaudhry and Marc Tremblay. This solution to the latency problem eliminates the complexity of the issue queue and the rename unit, and also achieves memory-level parallelism. However, it suffers from the disadvantage of having to re-compute any computational operations that are performed while in scout mode.

Hence, what is needed is a method and an apparatus for hiding memory latency without the above-described drawbacks of existing processor designs.

SUMMARY

One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. Next, the system executes the instruction and subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order. Upon encountering a store during the execute-ahead mode, the system determines if the store buffer is full. If so, the system prefetches a cache line for the store, and defers execution of the store.

In a variation on this embodiment, deferring the store involves inserting the store into a deferred queue, which contains deferred instructions in program order.

In a variation on this embodiment, after a store is deferred into the deferred queue during execute-ahead mode, if a load is subsequently encountered, the system prefetches a cache line for the load, and defers execution of the load to prevent a possible read-after-write (RAW) hazard.

In a variation on this embodiment, while executing the instruction and subsequent instructions in an execute-ahead mode, the store buffer is gated so that stores that enter the store buffer during execute-ahead mode remain in the store buffer until the processor leaves the execute-ahead mode.

In a variation on this embodiment, upon encountering a load during the execute-ahead mode, the system determines if a load buffer is full. If so, the system: prefetches a cache line for the load; defers execution of the load; and marks a destination register for the load to indicate that the value in the destination register is subject to an unresolved data dependency.

In a variation on this embodiment, if a non-data-dependent stall condition is encountered in normal execution mode, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the non-data-dependent stall condition. Next, the system enters a scout mode, wherein instructions are speculatively executed to prefetch future loads, but wherein results are not committed to the architectural state of the processor. When the non-data-dependent stall condition that caused the processor to move out of normal execution mode is finally resolved, the system uses the checkpoint to resume execution in normal execution mode from the instruction that originally encountered the stall condition.

In a variation on this embodiment, if a non-data-dependent stall condition that is not a load buffer full condition or a store buffer full condition is encountered in execute-ahead mode, the system enters a scout mode, wherein instructions are speculatively executed to prefetch future loads, but wherein results are not committed to the architectural state of the processor. When the unresolved data dependency or the non-data-dependent stall condition that originally caused the processor to move out of normal execution mode is finally resolved, the system uses the checkpoint to resume execution in normal execution mode from the instruction that originally encountered the stall condition.

In a variation on this embodiment, if the unresolved data dependency is resolved during execute-ahead mode, the system executes deferred instructions in a deferred mode. If all deferred instructions are executed during the deferred mode, the system returns to the normal execution mode to resume normal program execution from the point where the execute-ahead mode left off.

In a variation on this embodiment, executing deferred instructions in the deferred mode involves: issuing deferred instructions for execution in program order; deferring execution of deferred instructions that still cannot be executed because of unresolved data dependencies; and executing other deferred instructions that able to be executed in program order. If some deferred instructions are deferred again, the system returns to execute-ahead mode at the point where execute-ahead mode left off.

In a variation on this embodiment, executing instructions involves keeping track of data dependencies to facilitate determining if a given instruction is subject to an unresolved data dependency. This can involve maintaining state information for each register, which indicates whether or not a value in the register depends on an unresolved data-dependency.

In a variation on this embodiment, the unresolved data dependency can include: a use of an operand that has not returned from a preceding load miss; a use of an operand that has not returned from a preceding translation lookaside buffer (TLB) miss; a use of an operand that has not returned from a preceding full or partial read-after-write (RAW) from store buffer operation; and a use of an operand that depends on another operand that is subject to an unresolved data dependency.

In a variation on this embodiment, if the number of stores that are encountered during execute-ahead mode exceeds the capacity of the store buffer, which means that the store buffer will never have additional space to accept additional stores during the execute-ahead mode because the store buffer is gated, the system directly enters the scout mode, without waiting for the deferred queue to eventually fill.

In a variation on this embodiment, while executing deferred instructions in the deferred mode, if a deferred store is encountered, and the store buffer now has capacity because one or more stores that entered to store buffer prior to execute-ahead mode have left the store buffer, the system enters the deferred store into the store buffer instead of deferring the deferred store again. If no stores remain in the deferred queue, subsequent loads and stores are no longer forcefully deferred.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 illustrates a processor in accordance with an embodiment of the present invention.

FIG. 2 illustrates various buffers within a processor in accordance with an embodiment of the present invention.

FIG. 3 illustrates a register file in accordance with an embodiment of the present invention.

FIG. 4A illustrates a “store-in-DQ” indicator in accordance with an embodiment of the present invention.

FIG. 4B illustrates various counters for keeping track of stores during execute-ahead mode in accordance with an embodiment of the present invention.

FIG. 5 presents a state diagram, which includes execute-ahead mode and scout mode, in accordance with an embodiment of the present invention.

FIG. 6 presents a flow chart illustrating how a store is handled during execute-ahead mode in accordance with an embodiment of the present invention.

FIG. 7 presents a flow chart illustrating how a load is handled during execute-ahead mode in accordance with an embodiment of the present invention.

FIG. 8 presents a flow chart illustrating how the system directly enters scout mode when the number of stores encountered during execute-ahead mode exceeds the store buffer capacity in accordance with an embodiment of the present invention.

FIG. 9 presents a flow chart illustrating how a counter can be used to keep track of the number of stores in the deferred queue in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION

The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Processor

FIG. 1 illustrates the design of a processor 100 in accordance with an embodiment of the present invention. Processor 100 can generally include any type of processor, including, but not limited to, a microprocessor, a mainframe computer, a digital signal processor, a personal organizer, a device controller and a computational engine within an appliance. As is illustrated in FIG. 1, processor 100 includes instruction cache 102, fetch unit 104, decode unit 106, instruction buffer 108, deferred queue 112, grouping logic 110, main memory 124, arithmetic logic unit (ALU) 114, ALU 116, branch pipe 118 and floating point unit 120.

During operation, fetch unit 104 retrieves instructions to be executed from instruction cache 102, and feeds these instructions into decode unit 106. Decode unit 106 forwards the instructions to be executed into instruction buffer 108, which is organized as a FIFO buffer. Instruction buffer 108 feeds instructions in program order into grouping logic 110, which groups instructions together and sends them to execution units, including memory pipe 122 (for accessing main memory 124), ALU 114, ALU 116, branch pipe 118 (which resolves conditional branch computations), and floating point unit 120.

If an instruction cannot be executed due to an unresolved data dependency, such as an operand that has not returned from a load operation, the system defers execution of the instruction and moves the instruction into deferred queue 112. Note that like instruction buffer 108, deferred queue 112 is also organized as a FIFO buffer.

When the data dependency is eventually resolved, instructions from deferred queue 112 are executed in program order with respect to other deferred instructions, but not with respect to other previously executed non-deferred instructions. This process is described in more detail below with reference to FIG. 5.

Buffers

FIG. 2 illustrates various buffers within processor 100 in accordance with an embodiment of the present invention. These buffers include load buffer 201, store buffer 202 and prefetch buffer 203, which are well-known structures in existing processors. Also illustrated in FIG. 2 is a deferred queue 112 (from FIG. 1) and Level 2 (L2) cache 204.

Load buffer 201, store buffer 202 and prefetch buffer 203 hold entries for load, store and prefetch instructions that are waiting to access slower portions of the memory hierarchy, such as L2 cache 204 and possibly main memory 124.

The present invention exploits the instruction storage capacity of the deferred queue 112 to increase the effective size of load buffer 201 and store buffer 202. This is accomplished as follows. If load buffer 201 or store buffer 202 becomes full, additional loads or stores get deferred into deferred queue 112 as is described below with reference to FIGS. 3-9. All of this is accomplished without violating data flow dependencies.

Note that processor 100 needs to track when the load or store buffers are full. This can be done in several ways. For example, a credit mechanism can be employed in which credits are decremented upon issuing a load or store and the respective credit is returned when the load or store completes. Alternately, the load/store unit of processor 100 can signal the issue unit of processor 100 when it receives a load or store that would overflow one of its buffers. Regardless, the issue unit knows that the load or store could not be issued and so defers its execution by placing it into deferred queue 112.

Keeping Track of Dependencies

The present invention keeps track of data dependencies in order to determine if an instruction is subject to an unresolved data dependency. In one embodiment of the present invention, this involves maintaining state information for each register, which indicates whether or not a value in the register depends on an unresolved data dependency. For example, FIG. 3 illustrates a register file 302 in accordance with an embodiment of the present invention. Each register in register file 302 is associated with a “not-there” bit, which keeps track of whether a valid operand value is contained in the register, or if the operand cannot be produced because of an unresolved data dependency. For example, if a register is waiting for an operand to return from a load operation, the corresponding not-there bit is set to indicate that the desired operand value is not present in the register.

When a subsequent instruction references a source operand value that is marked as not-there, and generates a result that is stored in a destination register, the system marks the destination register as not-there to indicate that the value in the destination register also depends on the unresolved data-dependency. This can be accomplished by marking the not-there bit of the destination register with the “OR” of the not-there bits for source registers of the instruction.

Structures for Keeping Track of Stores

FIG. 4A illustrates a store-in-DQ indicator 402 in accordance with an embodiment of the present invention. Store-in-DQ indicator 402 is set whenever a store is deferred into deferred queue 112, and is cleared when all deferred stores are removed from deferred queue 112.

In another embodiment of the present invention, instead of maintaining a single store-in-DQ indicator 402, the system maintains a stores-in-DQ counter 404 and a stores-during-execute-ahead-mode counter 406 as is illustrated in FIG. 4B. Stores-in-DQ counter 404 keeps track of the number of stores in deferred queue 112, and hence, is a generalization of the store-in-DQ indicator 402. In contrast, stores-during-execute-ahead-mode counter 406 enables the system to determine if the number of stores that are deferred during execute-ahead mode exceed the capacity of the store buffer, and if so to immediately enter scout mode as is described in more detail below with reference to FIG. 8.

State Diagram

FIG. 5 presents a state diagram which includes execute-ahead mode 504 and the scout mode 508 in accordance with an embodiment of the present invention. The system starts in normal execution mode 502, wherein instructions are executed in program order as they are issued from instruction buffer 108 (see FIG. 1).

Next, if an unresolved data dependency arises during execution of an instruction, the system moves to execute-ahead mode 504. An unresolved data dependency can include: a use of an operand that has not returned from a preceding load miss; a use of an operand that has not returned from a preceding translation lookaside buffer (TLB) miss; a use of an operand that has not returned from a preceding full or partial read-after-write (RAW) from store buffer operation; and a use of an operand that depends on another operand that is subject to an unresolved data dependency.

While moving to execute-ahead mode 504, the system generates a checkpoint that can be used, if necessary, to return execution of the process to the point where the unresolved data dependency was encountered; this point is referred to as the “launch point.” (Generating the checkpoint involves saving the precise architectural state of processor 100 to facilitate subsequent recovery from exceptions that arise during execute-ahead mode 504 or deferred mode 506.) The system also “defers” execution of the instruction that encountered the unresolved data dependency by storing the instruction in deferred queue 112.

While operating in execute-ahead mode 504, the system continues to execute instructions in program order as they are received from instruction buffer 108, and any instructions that cannot execute because of an unresolved data dependency are deferred into deferred queue 112.

During execute-ahead mode 504, if an unresolved data dependency is finally resolved, the system moves into deferred mode 506, wherein the system attempts to execute instructions from deferred queue 112 in program order. Note that the system attempts to execute these instructions in program order with respect to other deferred instructions in deferred queue 112, but not with respect to other previously executed non-deferred instructions (and not with respect to deferred instructions executed in previous passes through deferred queue 112). During this process, the system defers execution of deferred instructions that still cannot be executed because of unresolved data dependencies by placing these again-deferred instruction back into deferred queue 112. On the other hand, the system executes other instructions that can be executed in program order with respect to each other.

After the system completes a pass through deferred queue 112, if deferred queue 112 is empty, the system moves back into normal execution mode 502. This may involve committing changes made during execute-ahead mode 504 and deferred mode 506 to the architectural state of processor 100, if such changes have not been already committed. It can also involve throwing away the checkpoint generated when the system moved into execute-ahead mode 504.

On the other hand, if deferred queue 112 is not empty after the system completes a pass through deferred queue 112, the system returns to execute-ahead mode 504 to execute instructions from instruction buffer 108 from the point where the execute-ahead mode 504 left off.

If a non-data dependent stall condition (except for a load buffer full or store buffer full condition) arises while the system is in normal execution mode 502 or in execute-ahead mode 504, the system moves into scout mode 508. (This non-data-dependent stall condition can include: a memory barrier operation; or a deferred queue full condition.) In scout mode 508, instructions are speculatively executed to prefetch future loads, but results are not committed to the architectural state of processor 100.

Scout mode 508 is described in more detail in a pending U.S. patent application entitled, “Generating Prefetches by Speculatively Executing Code Through Hardware Scout Threading,” by inventors Shailender Chaudhry and Marc Tremblay, having Ser. No. 10/741,944, and filing date 19 Dec. 2003, which is hereby incorporated by reference to describe implementation details of scout mode 508.

Unfortunately, computational operations performed during scout mode 508 need to be recomputed again, which can require a large amount of computational work.

When the original “launch point” stall condition is finally resolved, the system moves back into normal execution mode 502, and, in doing so, uses the previously generated checkpoint to resume execution from the launch point instruction that encountered the launch point stall condition. The launch point stall condition is the stall condition that originally caused the system to move out of normal execution mode 502. For example, the launch point stall condition can be the data-dependent stall condition that caused the system to move from normal execution mode 502 to execute-ahead mode 504, before moving to scout mode 508. Alternatively, the launch point stall condition can be the non-data-dependent stall condition that caused the system to move directly from normal execution mode 502 to scout mode 508.

Handling a Store in Execute-Ahead Mode

FIG. 6 presents a flow chart illustrating how a store is handled during execute-ahead mode 504 in accordance with an embodiment of the present invention. When a store is encountered during execute-ahead mode 504, the system checks store-in-DQ indicator 402 to determine whether there exists a deferred store in the deferred queue 112 (step 604). If so, a subsequent load cannot perform a CAM lookup on deferred queue 112, because unlike store buffer 202, deferred queue 112 lacks the circuitry to perform a CAM lookup. Hence, in order to avoid a potential read-after-write (RAW) hazard, the system defers subsequent loads.

Moreover, because of this deferral of younger loads, it is desirable for the first deferred store to enter store buffer 202 before a younger store. It is also preferable to keep the space in store buffer 202 free, so that upon entering deferred mode 506 the first such deferred store will enter store buffer 202. Hence, instead of executing a subsequent store that follows the first deferred store, the system defers the subsequent store by prefetching the subsequent store (step 608) and inserting the subsequent store into deferred queue 112 (step 610).

Note that store-in-DQ indicator 402 cannot be immediately cleared if a store should complete and free up an entry in the store buffer. Once a store is deferred because of lack of space in store buffer 202, all younger loads in program order must be deferred. Thus, store-in-DQ indicator 402 remains set until processor 100 enters deferred mode 506. At this point the store-in-DQ indicator 402 is cleared. If store buffer 202 is still full, the store that was originally deferred will be deferred again, and system will again set store-in-DQ indicator 402.

On the other hand, if there no longer exists a deferred store in deferred queue 112 at step 604, the system determines if store buffer 202 is full (step 606). If so, the system defers the store by prefetching the store (step 608) and inserting the store into deferred queue 112 (step 610). The system also sets store-in-DQ indicator 402 (if it is not already set), or alternatively increments stores-in-DQ counter 404. Otherwise, if store buffer 202 is not full, the system processes the store normally in execute-ahead mode 504, which involves placing the store into store buffer 202 (step 612).

Handling a Load in Execute-Ahead Mode

FIG. 7 presents a flow chart illustrating how a load is handled during execute-ahead mode 504 in accordance with an embodiment of the present invention. When a load is encountered during execute-ahead mode 504, the system checks store-in-DQ indicator 402 to determine whether there exists a deferred store in the deferred queue 112 (step 704). If so, in order to avoid a potential RAW hazard, the system defers the load by prefetching the load (step 708) and inserting the load into deferred queue 112 (step 710).

On the other hand, if there does not exist a deferred store in deferred queue 112 at step 704, the system determines if load buffer 201 is full (step 706). If so, the system defers the load by prefetching the load (step 708) and inserting the load into deferred queue 112 (step 710). Otherwise, if the load buffer is not full, the system processes the load normally in execute-ahead mode 504, which involves placing the load into load buffer 201 (step 712).

Note that when a load is deferred, its destination register is marked as “not-there.” Furthermore, note that the previously-described mechanism for propagating not-there bits works naturally to avoid RAW hazards.

Entering Scout Mode Directly

FIG. 8 presents a flow chart illustrating how the system directly enters scout mode 508 when the number of stores encountered during execute-ahead mode 504 exceeds the capacity of store buffer 202 in accordance with an embodiment of the present invention. During execute-ahead mode 504, the system increments stores-during-execute-ahead-mode counter 406 for every store the system encounters (step 802). The system then determines if stores-during-execute-ahead-mode counter 406 exceeds the capacity of store buffer 202 (step 804).

If so, store buffer 202 will eventually fill with stores encountered during execute-ahead mode 504. Note that these stores will never leave store buffer 202 because store buffer 202 is gated during execute-ahead mode 504. Furthermore, at least one additional store will remain in deferred queue 112. This additional store will never leave deferred queue 112 because there will never be space for it is store buffer 202. Hence, execute-ahead mode 504 will never complete successfully, and deferred queue 112 will eventually fill up with instructions, which will cause the system to enter scout mode 508. Instead of waiting for deferred queue 112 to fill up, one embodiment of the present invention immediately enters scout mode 508 because the system will eventually have to enter scout mode 508 anyway (step 806). Note that the system does not have to always enter scout mode 508 at this point, but can instead decide heuristically whether to stall issue or to immediately enter scout mode 508.

Otherwise, if stores-during-execute-ahead-mode counter 406 does not exceed the capacity of store buffer 202, the system returns to step 802 to resume normal operation in execute-ahead mode 504.

Keeping Track of Stores in the Deferred Queue

FIG. 9 presents a flow chart illustrating how stores-in-DQ counter 404 can be used to keep track of the number of stores in deferred queue 112 in accordance with an embodiment of the present invention. For each store that is deferred during execute-ahead mode 504, the system increments stores-in-DQ counter 404 (step 902).

While retrying deferred stores in deferred mode 506, if a deferred store can be placed in store buffer 202 (for example, because there is space in store buffer 202, or because a preceding deferred store has completed), the system executes the store in deferred mode 506. This involves placing the store into store buffer 202 and decrementing stores-in-DQ counter 404 (step 904).

If stores-in-DQ counter 404 reaches zero, no stores remain in deferred queue 112. Consequently, subsequent loads and stores do not have to be forcefully deferred into deferred queue 112 (step 906).

The foregoing descriptions of embodiments of the present invention have been presented only for purposes of illustration and description. They are not intended to be exhaustive or to limit the present invention to the forms disclosed. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. Additionally, the above disclosure is not intended to limit the present invention. The scope of the present invention is defined by the appended claims. 

1. A method for deferring a store and generating a prefetch when a store buffer in a processor becomes full during program execution in an execute-ahead mode, comprising: issuing instructions for execution in program order during a normal execution mode; upon encountering an unresolved data dependency during execution of an instruction, generating a checkpoint that can subsequently be used to return execution of the program to the point of the instruction, and executing the instruction and subsequent instructions in the execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order; upon encountering a store during the execute-ahead mode, determining if the store buffer is full, if the store buffer is full, prefetching a cache line for the store, and deferring execution of the store, and if the store buffer is not full, executing the store; and upon encountering a non-data-dependent stall condition in normal execution mode, generating a checkpoint that can subsequently be used to return execution of the program to the point of the non-data-dependent stall condition; entering a scout mode, wherein instructions are speculatively executed to prefetch future loads, but wherein results are not committed to the architectural state of the processor; and when the non-data-dependent stall condition that caused the processor to move out of normal execution mode is finally resolved, using the checkpoint to resume execution in normal execution mode from the instruction that originally encountered the stall condition.
 2. The method of claim 1, wherein deferring the store involves inserting the store into a deferred queue, which contains deferred instructions in program order.
 3. The method of claim 2, wherein after a store is deferred into the deferred queue during execute-ahead mode, if a load is subsequently encountered, the method further comprises: prefetching a cache line for the load, and deferring execution of the load to prevent a possible read-after-write (RAW) hazard.
 4. The method of claim 1, wherein while executing the instruction and subsequent instructions in an execute-ahead mode, the store buffer is gated so that stores that enter the store buffer during execute-ahead mode remain in the store buffer until the processor leaves the execute-ahead mode.
 5. The method of claim 1, wherein upon encountering a load during the execute-ahead mode, the method further comprises: determining if a load buffer is full; if the load buffer is full, prefetching a cache line for the load, deferring execution of the load, and marking a destination register for the load to indicate that the value in the destination register is subject to an unresolved data dependency; and if the load buffer is not full, executing the load.
 6. The method of claim 1, wherein if a non-data-dependent stall condition that is not a load buffer full condition or a store buffer full condition is encountered in execute-ahead mode, the method further comprises: entering a scout mode, wherein instructions are speculatively executed to prefetch future loads, but wherein results are not committed to the architectural state of the processor; and when the unresolved data dependency or the non-data-dependent stall condition that originally caused the processor to move out of normal execution mode is finally resolved, using the checkpoint to resume execution in normal execution mode from the instruction that originally encountered the stall condition.
 7. The method of claim 1, wherein if the unresolved data dependency is resolved during execute-ahead mode, the method further comprises: executing deferred instructions in a deferred mode; and upon all deferred instructions being executed, returning to the normal execution mode to resume normal program execution from the point where the execute-ahead mode left off.
 8. The method of claim 7, wherein executing deferred instructions in the deferred mode involves: issuing deferred instructions for execution in program order; deferring execution of deferred instructions that still cannot be executed because of unresolved data dependencies; and executing other deferred instructions that are able to be executed in program order.
 9. The method of claim 8, wherein if some deferred instructions are deferred again, the method further comprises returning to execute-ahead mode at the point where execute-ahead mode left off.
 10. The method of claim 1, wherein executing instructions involves keeping track of data dependencies to facilitate determining if a given instruction is subject to an unresolved data dependency.
 11. The method of claim 10, wherein keeping track of data dependencies involves maintaining state information for each register, which indicates whether or not a value in the register depends on an unresolved data-dependency.
 12. An apparatus that defers a store and generates a prefetch when a store buffer in a processor becomes full during program execution in an execute-ahead mode, comprising: an execution mechanism configured to issue instructions for execution in program order during a normal execution mode; wherein upon encountering an unresolved data dependency during execution of an instruction, the execution mechanism is configured to, generate a checkpoint that can subsequently be used to return execution of the program to the point of the instruction, and to execute the instruction and subsequent instructions in the execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order; wherein upon encountering a store during the execute-ahead mode, the execution mechanism is configured to, determine if the store buffer is full, if the store buffer is full, to prefetch a cache line for the store, and defer execution of the store, and if the store buffer is not full, to execute the store; and wherein upon encountering a non-data-dependent stall condition in normal execution mode, the execution mechanism is configured to, generate a checkpoint that can subsequently be used to return execution of the program to the point of the non-data-dependent stall condition; enter a scout mode, wherein instructions are speculatively executed to prefetch future loads, but wherein results are not committed to the architectural state of the processor; and when the non-data-dependent stall condition that caused the processor to move out of normal execution mode is finally resolved, to use the checkpoint to resume execution in normal execution mode from the instruction that originally encountered the stall condition.
 13. The apparatus of claim 12, wherein deferring the store involves inserting the store into a deferred queue, which contains deferred instructions in program order.
 14. The apparatus of claim 13, wherein after a store is deferred into the deferred queue during execute-ahead mode, if a load is subsequently encountered, the execution mechanism is configured to: prefetch a cache line for the load, and to defer execution of the load to prevent a possible read-after-write (RAW) hazard.
 15. The apparatus of claim 12, wherein while executing the instruction and subsequent instructions in an execute-ahead mode, the store buffer is gated so that stores that enter the store buffer during execute-ahead mode remain in the store buffer until the processor leaves the execute-ahead mode.
 16. The apparatus of claim 12, wherein upon encountering a load during the execute-ahead mode, the execution mechanism is configured to: determine if a load buffer is full; if the load buffer is full, to prefetch a cache line for the load, defer execution of the load, and to mark a destination register for the load to indicate that the value in the destination register is subject to an unresolved data dependency; and if the load buffer is not full, to execute the load.
 17. The apparatus of claim 12, wherein if a non-data-dependent stall condition that is not a load buffer full condition or a store buffer full condition is encountered in execute-ahead mode, the execution mechanism is configured to: enter a scout mode, wherein instructions are speculatively executed to prefetch future loads, but wherein results are not committed to the architectural state of the processor; and when the unresolved data dependency or the non-data-dependent stall condition that originally caused the processor to move out of normal execution mode is finally resolved, to use the checkpoint to resume execution in normal execution mode from the instruction that originally encountered the stall condition.
 18. A computer system that defers a store and generates a prefetch when a store buffer in a processor becomes full during program execution in an execute-ahead mode, comprising: the processor; a memory an execution mechanism within the processor, which is configured to issue instructions for execution in program order during a normal execution mode; wherein upon encountering an unresolved data dependency during execution of an instruction, the execution mechanism is configured to, generate a checkpoint that can subsequently be used to return execution of the program to the point of the instruction, and to execute the instruction and subsequent instructions in the execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order; wherein upon encountering a store during the execute-ahead mode, the execution mechanism is configured to, determine if the store buffer is full, if the store buffer is full, to prefetch a cache line for the store, and defer execution of the store, and if the store buffer is not full, to execute the store; and wherein upon encountering a non-data-dependent stall condition in normal execution mode, the execution mechanism is configured to, generate a checkpoint that can subsequently be used to return execution of the program to the point of the non-data-dependent stall condition; enter a scout mode, wherein instructions are speculatively executed to prefetch future loads, but wherein results are not committed to the architectural state of the processor; and when the non-data-dependent stall condition that caused the processor to move out of normal execution mode is finally resolved, to use the checkpoint to resume execution in normal execution mode from the instruction that originally encountered the stall condition. 